In a complex integrated circuit (IC), the shrinkage of the devices thereof makes the design more difficult. Process such as selfalignment and other techniques are used for the desired designs.
FIG. 1 shows a cross-sectional view of a gate structure 10 in a typical flash memory, in which a tunnel oxide 14 is formed on a substrate 12 with a floating gate polysilicon layer 16 thereon, and an oxide-nitride-oxide (ONO) layer 18 is further formed on the polysilicon layer 16 with a control gate polysilicon layer 20 thereon. Moreover, a control gate tungsten silicide layer 22 and a hard mask layer 24 are formed on the polysilicon layer 20, and a source 30 and a drain 32 are formed on the substrate 12. In the formation of the gate structure 10, deposition and etching processes are used to obtain a gate stack on the substrate 12. Then selfaligned process with the gate stack as a mask is used to form the source 30 and drain 32. After forming the spacers 26 and 28, a selfaligned process is further used to form source and drain contacts. Prior arts are proposed for such selfaligned processes, such as in U.S. Pat. Nos. 5,907,781 and 6,444,530 issued to Chen et al.
However, due to the tungsten silicide layer sandwiched in the gate structure, the critical dimension (CD) will be enlarged and the distances between the gate and the contact windows of the source and drain will be shortened by the thermal expansion of the tungsten silicide layer resulted from the thermal stress when the crystal structure of the tungsten silicide is transferred from tetragon cubic to hexagon cubic in the subsequent thermal process, such as oxidation and annealing. In addition, the breakdown voltage of the structure is lower for the shortage of spaces therebetween. Further, the re-growth of the tungsten silicide grain squeezes each other and causes the sidewall of the gate structure rough and uneven, and as a result, the local electric filed effect is enhanced and induces unpredicted discharge at sharp corners to damage the gate structure and shorten the lifetime of the flash memory. It is therefore desired a selfaligned process to obtain gate structure having a flat sidewall for flash memories.